In personal computer systems, the AT interface is widely used to connect a host with its peripheral devices. A HDD is a typical peripheral device. From a viewpoint of peripheral manufacturers, it is desired that communications with a host through the AT interface be standardized, but some commands allow more than one operation sequence. For example, a Read command for an HDD is executed in either one of two operation sequences depending on when a status register of the HDD is read by the host. The first operation sequence is as follows:
1. When data (usually in one sector) becomes ready to be transferred to the host, the HDD sets a data request (DRQ) bit of the status register high and at the same time asserts an interrupt request IRQ to the host.
2. Receiving the IRQ from the HDD, the host first reads the status register of the HDD (The IRQ is reset or dropped at that time. The IRQ is always reset whenever the status register is read by the host), and then starts a data transfer.
3. When the transfer of a sector of data is completed, the HDD once resets the DRQ bit.
4. Steps 1 to 3 are repeated for the requested number of sectors.
In the above sequence, the host reads the status register before the data transfer is started, and therefore, the sequence is hereinafter referred to as "pre-read". However, some hosts handle the Read command as follows:
1. Same as Step 1 of the pre-read.
2. Receiving the IRQ from the HDD, the host first starts a data transfer which continues till the end of that sector.
3. Same as Step 3 of the pre-read.
4. The host reads the status register of the HDD (the IRQ is reset thereby).
5. Steps 1 to 4 are repeated for the requested number of sectors.
In the second sequence, the host reads the status register after the transfer of a sector of data is completed, and therefore, this sequence is hereinafter referred to as "post-read". If the host operates in a post-read mode, a malfunction would occur in the case where the host attempts to read the status register of the HDD to obtain the current sector status (Step 4 of the post-read) after the next sector of data becomes ready to be transferred in the HDD (Step 1 following Step 4). In this case, an IRQ for the next sector is reset by the status register reading for the previous sector transfer, which results in an abnormal situation where the host continues to wait for the IRQ for the next sector while the HDD continues to wait for the data transfer. In fact, such abnormal situation has occurred, since the IRQ for the next sector is asserted by hardware as soon as the sector data becomes available.
To avoid the abnormal situation described above, it is necessary to assert the IRQ for the next sector after the host reads the status register. However, since the above abnormal situation will not occur when the host is in the pre-read mode, a scheme to merely delay the IRQ would cause a problem that the performance of data transfer is lowered when the host is in the pre-read mode. Therefore, the prior art has adopted a method in which a switch is set according to whether the host is in the pre-read mode or the post-read mode and, in case of the post-read, the IRQ is asserted again immediately after the status register is read instead of delaying the IRQ. Thus, the performance is not lowered even in case of the post-read. However, in modern hosts, there are many cases where either one of the pre-read and post-read modes is used depending on an operating system (OS) (for example, the pre-read and post-read modes are used under OS/2 and conventional DOS, respectively) and therefore the switch must be set each time of mode change.
Another method uses a microcode to entirely control the IRQ. According to the method, since the IRQ is always asserted late, both the pre-read and post-read modes function normally while the performance is not good as compared with the hardware control.
To solve the problems as described above, Japanese Patent Application No. 3-337995, which is a prior application of the present assignee, discloses an interface circuit that automatically detects whether the host is in the pre-read mode or the post-read mode. The interface circuit includes a mode detecting circuit for automatically detecting a mode of the host according to the states of a data request signal DRQ from a controller of the HDD and an interrupt request signal IRQ to be transmitted to the host, a delay circuit for delaying the DRQ by a predetermined amount of time when the host is in the post-read mode, and an interrupt request generating circuit for generating an IRQ to the host in response to an output (controlled DRQ) from the delay circuit. When the mode detecting circuit detects that the host is in the pre-read mode, the delay circuit does not operate and the DRQ is provided, without delay, to the interrupt request generating circuit as a controlled DRQ.
When the above interface circuit is used, performance is improved as compared with the conventional methods for changing by the switch and for controlling by the microcode, but there is a problem that an IRQ cannot be immediately generated even if the host has completed the status reading before the predetermined delay time elapses since the delay time of the DRQ is previously fixed.